library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity mux_2_1 is
	generic(
		nBit : natural := 32
	);
	port(
		A : in std_logic_vector(nBit-1 downto 0);
		B : in std_logic_vector(nBit-1 downto 0);
		sel : in std_logic;
		output : out std_logic_vector(nBit-1 downto 0)
	);
end entity;

architecture behavioral of mux_2_1 is

signal internal_output : std_logic_vector(nBit-1 downto 0);

begin
	P1 : process (A, B, sel)
	begin
		if sel = '0' then
			internal_output <= A;
		else
			internal_output <= B;
		end if;
	end process;
	output <= internal_output;
end behavioral;